Nano scale NAND flash memory, 3 bit per cell, 3D NAND structure

◈ Title : Nano scale NAND flash memory, 3 bit per cell, 3D NAND structure
◈ Speaker : Principal engineer. Myoung Kwan, Cho (Hynix)
◈ Date & Time : Friday, April 8, 2011 (14:00pm ~ 15:30pm)
◈ Place : LG Research Building, Room #101
◈ Host : Prof.  Jeong-Soo, Lee  (Tel. 2380)
◈ Abstract : Recent NAND flash memory technology is presented, especially in terms of 3 bit per cell and 3D NAND structure. In the 2xnm era,  NAND cell scaling down have faced process complexity and narrow cell operation window. In this presentation, the operation algorithm in 3 bit per cell and the characteristics of 3D NAND cell is discussed.