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  • The Crystal Ball of Technology: towards a roadmap for innovation

    ▣ Title : The Crystal Ball of Technology: towards a roadmap for innovation
    ▣ Speaker : Kamran Eshraghian (President of iDataMap)  
    ▣ Time : Friday, September 21, 2012 (2:00pm-3:30pm)
    ▣ Place : Room #101, LG Research Bldg.
    ▣ Hosted by : Prof. Young Hwan Kim (Tel. 279-2227)
    ▣Abstract : The thought provoking possibilities of neuroscientists offering an insight into the fascinating functions of the more recently discovered “mirror neurons” some of which appear to have formed the foundations of human interaction and the learning processes; and then the “adaption principle” that provides a glimpse into the processing capability of the brain in selective tuning of the unwanted encountered in our daily routines, makes all the rights and wrongs of the new frontiers of smart products well worth the effort. This presentation by the way of examples will highlight the evolutionary nature of progress in technology and will highlight the changes that have taken place during the last decade in the market place primarily are driven by innovators. Some focus will be placed upon the panacea for a new model that would facilitate growth between research and educational sectors and business.  Essential attributes of the technology roadmap that span from simple circuit elements through to complex visual computational engines such as those of an insect vision and then possibilities in the deployment of “mirror neurons” will be explored, thus providing the rational as to why we need innovators in business.
      Prof. Kamran Eshraghian is very well known as the co-author of the best-seller textbook, “Principles of CMOS VLSI Design: a systems perspective”, used by over 800 universities.
     He is also world-famous for his top-notch speeches to inspire creative minds into young students.

     

  • 항공전자/비행제어 기술발전 방향 / Technical Trend of Avionics & Flight Control

    ▣ Title : 항공전자/비행제어 기술발전 방향 / Technical Trend of Avionics & Flight Control   
    ▣ Speaker : 송찬호 부장 (국방과학연구소) / Chan Ho Song, Ph.D. (Agency for Defense Development)
    ▣ Time : 2012년 5월 11일(금) 오후 2:00~3:30 / pm14:00~15:30, May 11 (Fri)
    ▣ Place : LG동 강당 (101호) / Room #101, LG Research Bldg.
    ▣ Hosted by : 이진수 교수 (T. 279-2230) / Prof. Jin Soo Lee (Tel. 279-2230)   
        BK21 미래정보기술사업단 / BK21 Educational Institute of Future Information Technology
    ▣Abstract : 항공기, 특히 군용 항공기를 중심으로 항공전자/비행제어 기술에 대한 현황과 발전 방향을 살펴 본다. 
    항공기 항공전자/비행제어 기술은 전자 산업과 IT기술의 급속한 성장에 힘입어 놀랍게 발전하고 있다. 항공전자 분야의 핵심기술로는 통합 모듈형 (Integrated modular) 으로의 항전체계 통합기술 (Tecnology of integrated avionics), 조종사-항공기 연동 기술(Human-Computer Interaction), 무인자율화 기술 등을 들 수 있다.
     비행제어 분야는 전자식 비행제어 (Fly-By-Wire) 시스템의 출현으로 비행체 안정성보다는 제어성에 더욱 치중할 수 있게 되면서 다양하게 성능을 발전시켜 가고 있다.
     핵심기술로는 추력편향제어, 고앙각 영역에서의 비행제어, 정적으로 불안정한 비행체에 대한 능동 제어, Active flow Control, Cooperative control, 자동착륙 기술(무인기), 무장발사/기동 최적화 기술 등을 들 수 있으며, 현대제어 이론(비선형 제어, 적응제어, 강인제어 이론 등)의 도움으로 성능을 더욱 향상시키려는 노력이 지속되고 있다.
     이러한 항공전자/비행제어 기술 발전 추세를 살펴보고 국내기술을 발전시키기 위한 로드맵을 제시해 본다.

     

  • PRAM: Application-Driven Technology and Its Future

    ▣ Title : PRAM: Application-Driven Technology and Its Future  
    ▣ Speaker : 하대원 박사 (삼성전자) / Dae won Ha, Ph.D. (Samsung Electronics)
    ▣ Time : 2012년 5월 4일(금) 오후 2:00~3:30 / pm14:00~15:30, May 4 (Fri)
    ▣ Place : LG동 강당 (101호) / Room #101, LG Research Bldg.
    ▣ Hosted by : 이정수 교수 (T. 279-2380) / Prof. Jeong Soo Lee (Tel. 279-2380)   
        BK21 미래정보기술사업단 / BK21 Educational Institute of Future Information Technology
    ▣ Abstract : 
    Recently, great advances in PRAM (Phase-change Random Access Memory) cell technology have been accomplished; scalability down to 3nm [1,2], memory capacity up to 8 Gb [3], 2 bit MLC (Multi-Level Cell) operation [4], and reliabilities [5,6].
    In this seminar, the unique features of PRAM will be discussed by comparing its cell operation and array operation with those of a conventional DRAM and NAND flash memory. Then, the recent progress of PRAM will be discussed, mainly focusing on its potential applications to the code storage memory, data storage cache memory, data storage memory, and main memory. Also, the future PRAM research and development direction will be projected.

    [1]  J. Liang et al., VLSI Tech, pp. 100-101, 2011
    [2]  F. Xiong et al., SCIENCE, Vol. 332, pp. 568-570, Apr 2011.
    [3]  Y.D. Choi et al., ISSCC, accepted for publication, 2012.
    [4]  G.F. Close et al., VLSI Tech, pp. 202-203, 2011
    [5]  A.L. Lacaita et al., IEDM, pp. 157-160, 2007.
    [6]  S.J. Ahn et al., IEDM, pp. 295-298, 2011.

  • Genetically Engineering Energy Devices

    ▣ Title : Genetically Engineering Energy Devices
    ▣ Speaker : 이현정 박사 (한국과학기술연구원) / Hyunjung Yi, Ph.D. (Korea Institute of Science and Technology)
    ▣ Time : 2012년 4월 27일(금) 오후 2:00~3:30 / pm14:00~15:30, April 27 (Fri)
    ▣ Place : LG동 강당 (101호) / Room #101, LG Research Bldg.
    ▣ Hosted by : 김병섭 교수 (T. 279-2382) / Prof. Byung Sub Kim (Tel. 2382)   
        BK21 미래정보기술사업단 / BK21 Educational Institute of Future Information Technology
    ▣ Abstract : 
    Making nanocomposites from combinations of materials each with their own unique functional advantage can often solve issues that cannot be addressed when utilizing only one type of materials. Therefore, controlling nanostructure and nanoarchitecture have become central issues in energy devices such as high-power rechargeable batteries and highly efficient solar cells whose performance requires several different material properties. Biological systems can provide precise control over materials interaction between peptides and other non-biological materials through biological molecular recognition, and the capability of modifying and controlling materials interaction through genetic engineering provides an attractive route to creating new nano-structured hybrid materials systems. In this talk, new approaches to effectively incorporating single-walled carbon nanotubes (SWNTs) into nanostructures will be presented. Genetically engineered M13 virus clones are developed to assemble SWNTs and technically important inorganic materials biomineralized on the protein surfaces of M13 virus to create hybrid nanostructured electrodes for high-power Li-ion batteries and highly efficient dye-sensitized solar cells. The fundamental understanding and new approaches this work presents will provide new insight into designing materials for high performance energy devices.

     

  • On the Design of Secure Codes at Finite Lengths for Wiretap Channel

    ▣ Title : On the Design of Secure Codes at Finite Lengths for Wiretap Channel
    ▣ Speaker : Prof. Jeongseok Ha (KAIST)
    ▣ Time : Friday, September 14, 2012 (2:00pm-3:30pm)
    ▣ Place : Room #101, LG Research Bldg.
    ▣ Hosted by : Prof. Bumman Kim (Tel. 279-2231)
    ▣ Abstract : 
    Ozarow and Wyner proposed a secrecy code design scheme using a linear code and its cosets. It was shown that when a wiretap channel has a noiseless main channel and an eavesdropper taps a subset of coded bits through a wiretapper’s channel, the eavesdropper’s equivocation is readily obtained by analyzing a parity-check matrix of the linear code. However, for wiretap codes at finite lengths, the complexity to find the equivocation grows rapidly and becomes prohibitive with the increasing length of codewords. In this talk, we introduce a tight lower bound on the equivocation that can be available by simple manipulations when a secrecy code is transmitted over a perfect-BEC wiretap channel of type-I. The lower bound provides a guaranteed secrecy performance for various linear codes at any lengths over perfect-BEC wiretap channels of type-I. It will be demonstrated that the lower bound can be applied to design of secrecy codes for wiretap channels of type-I with Gaussian main and wiretapper’s channels.
     In this talk, we also discuss a binary erasure wiretap channel of type II in which the number of eavesdropped bits becomes available a posteriori. We aim at achieving perfect secrecy over such a channel model. The most appropriate application is a secret key agreement scheme. We present a secret key agreement scheme that adopts the formulation S = HX of Wyner-Ozarows’s linear coset coding. The scheme is based on the following simple observation: even if some information on a secret message S leaked out, it is still possible to have perfect secrecy for some subsequence of S. Our secret key agreement scheme achieves perfect secrecy by taking only those subsequences that are independent of the eavesdropped bits. Our secret key agreement scheme naturally leads to defining a security measure D for parity-check matrices such that the eavesdropper gets zero information on the subsequence as long as the length of the subsequence is less than the security measure D. Possible applications of the key agreement scheme will also be introduce.

  • Trends of Radar technologies and development process

     
    Title : Trends of Radar technologies and development process
    Speaker : Soo Hong Kim, Director (LIG Nex1 ISR Research Center)
    Time : Friday, May 25, 2012 (2:00pm-3:30pm)
    Place : Room #101, LG Research Bldg.
    Hosted by : Prof. Kyung-Tae Kim (Tel. 279-2381)
     Abstract : 
    In this presentation, I will introduce two topics about radar system development. In the first topic, the basic concept of radar system and required technologies are presented. The radar transmits high power microwave signal to space, receives echo signal from target, and extract information of targets. The technology characteristics of radar system include big antenna, high power of amplifier, high dynamic range of a receiver, and high speed signal processing. He talks also new trends and technology about radar. The second is how we can develop radar systems. Radar is very complex system and radar development is not simple. Technologies are very important, but there are more things for radar development, such as time schedule, budget, performance, trade-off issue, and/or people management problem. I will introduce system engineering (SE) and the radar development process with some examples based on the experience of radar development program in LIG Nex1.

     

  • Coordination in Mobile-manipulators

    ▣ Title : Coordination in Mobile-manipulators
    ▣ Speaker : 이장명 교수 (부산대학교) / Prof. Jang Myung Lee (Pusan University)
    ▣ Time : 4. 20(금) 오후 2:00~3:30 / pm14:00~15:30, April 20 (Fri)
    ▣ Place : LG동 강당 (101호) / Room #101, LG Research Bldg.
    ▣ Hosted by : 원상철 교수 (T. 279-2221) / Prof. Sang Chul won (T. 279-2221)   
        BK21 미래정보기술사업단 / BK21 Educational Institute of Future Information Technology
    ▣ Abstract : 
     The coordination between the mobile robot and manipulators have been discussed in detail.
    Through the visual feedback, the end-effector of the manipulator can be controlled to the desired position with a desired configuration.
     While it is moving there are several factors to be considered: energy, torque, time, and efficiency. All those factors are combined to select an optimal posture for the manipulators for a given task.
     The control of the mobile robot needs to be concerned with the configuration of the manipulators to keep the balance.
     The coordination between the mobile robot and the manipulators is required to cope with these requirements.
     Some preliminary experimental results will be demonstrated.

     

  • Software Solutions to Hardware Problems in the Billion-Transistor Era

    ▣ Title : Software Solutions to Hardware Problems in the Billion-Transistor Era
    ▣ Speaker : 이재욱 교수 (성균관대학교) / Prof. Jae W. Lee (SungKyunKwan University)
    ▣ Time : 4. 13(금) 오후 2:00~3:30 / pm14:00~15:30, April 13 (Fri)
    ▣ Place : LG동 강당 (101호) / Room #101, LG Research Bldg.
    ▣ Hosted by : 김병섭 교수 (T. 279-2382) / Prof. Byung Sub Kim (T. 279-2382)   
        BK21 미래정보기술사업단 / BK21 Educational Institute of Future Information Technology
    ▣ Absteact : 
    The computer industry’s success for the past three decades has been primarily driven by Moore’s Law, which states a long-term technology trend of the transistor count on a chip doubling every two years. The exponential increase in transistor count implies an exponential reduction in transistor size, which makes modern processor design more challenging than ever. With operating voltage remaining relatively constant, high-performance single-core processors hit a physical limit on the amount of power a chip can dissipate, called the Power Wall. This has caused an end to exponential increases in clock frequencies and forced an industry-wide shift to multicores. However, multicores are only a half solution to the problem since the difficult task of extracting and exploiting parallelism should be handled by software. In this talk, I will first present recent progress in software-only speculative pipeline parallelization and run-time parallelism adaptation to achieve scalable and robust performance on multicores. If time permits, I will also briefly introduce software-only techniques to improve fault tolerance in modern microprocessors.